Double-Dabble Algorithm on FPGA. Converting number to digits, i.e. to BCD notation - FPGA Stream #50

FPGA implementation of Double-Dabble Algorithm (stream just for fun). In computer science, the double dabble algorithm is used to convert binary numbers into binary-coded decimal (BCD) notation. It is also known as the shift-and-add-3 algorithm, and can be implemented using a small number of gates in computer hardware. -- -- Присоединяйтесь к комьюнити FPGA/ПЛИС разработчиков -- Стримы проходят каждую субботу -- Прочее Тайминги #doubledabble