Pre-layout signal integrity simulation of DDR4 nets with LineSim of HyperLynx SI ALT

LineSim feature of the HyperLynx SI ALT bundle allows running a proper pre-layout simulation helping to avoid unnecessary problems with the design. Using it helps to find the most reliable termination configuration and optimize the PCB layout upfront. Sintecs BV is a professional developer of high-speed electronics operating on the market since 2000. The company provides PCB design, signal integrity, power integrity, embedded software development services. The main office is in Hengelo, the Netherlands, with an R&D office in Vilnius, Lithuania.