SDRA2020 - 03/04 - Laurence Barker: Using Xilinx Vivado for SDR Development

This paper presents my incomplete work to develop an SDR transceiver compatible with the HPSDR projects. The work has been inspired by that of Pavel Demin but it is not a copy. Xilinx “Vivado” FPGA firmware tools include the IP Integrator. This tool allows a design to be implemented as a visual block diagram, with functional blocks joined together to create the overall flow graph. Functional blocks can be picked from a library, or can be written using VHDL or Verilog. A wide range of DSP functional blocks are provided. Important enablers for the block design approach are the AXI Bus and AXI Stream interconnect. The paper describes the AXI Stream, and how it enables DSP modules to be interconnected easily. I present my flow graph for an SDR receiver and transmitter module implemented using IP integrator, and demonstrate using IP integrator. I demonstrate using the simulator to test parts of the block design, followed by the code running on Xilinx hardware. The simulator allows gate-level simulation, but the block diagram sometimes needs to be redrawn to get access to the signals required. Camera & Edit: FurStreaming Sebastian, DL5WN Marc, DO1BOL Torben